2024-04-25
- beijing|| ||
- 1-3 years
- Junior college or above
- Full time
- 1
Responsibilities
1. Design and integrate peripheral interface blocks like I2C, I2S, UART, SPI, etc.
2. Design clock and reset in module level and system level;
3. Responsible for design specification writing, RTL quality check, module level and chip level synthesis;
4. Work with software and algorithm team to define module function, SW/HW interface, system test;
5. Work with verification team in module simulation, function coverage and code coverage check.
Requirements
1.BS or MS degree in EE, CS, telecom, Microelectronics etc.;
2. Proficient in Verilog/SystemVerilog;
3.Good communication skill, team player with responsibility and passion。
Quick navigation
Contact Us
Tel:010-85160285
Email:service@ingchips.com
Resume delivery:hr@ingchips.com
Office
Beijing:Room 803, Building #3, Zijin Digital Park, Haidian District
Shanghai:Room 316, Tower A, Juxin Building, Xiangke Road #58
Shenzhen:Room 1009, Shuguang Building, Science Park, Nanshan District
Copyright:Ingchips Technology Co., Ltd. 苏ICP备2022018764号-2 BY : xinnet